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ht48ra1/HT48CA1 remote type 8-bit mcu rev. 1.30 1 october 12, 2007 general description the ht48ra1/HT48CA1 are 8-bit high performance, risc architecture microcontroller devices specifically designed for multiple i/o control product applications. the data rom can be used to store remote control codes. the mask version HT48CA1 is fully pin and func - tionally compatible with the otp version ht48ra1 de - vice. the advantages of low power consumption, i/o flexibil- ity, timer functions, oscillator options, watchdog timer, programmable frequency divider, halt and wake-up functions, as well as low cost, enhance the versatility of these devices to suit a wide range of application possi - bilities such as industrial control, consumer products, subsystem controllers, and particularly suitable for use in products such as universal remote controller (urc). features operating voltage: 2.0v~5.5v 23 bidirectional i/o lines (max.) 1 interrupt input shared with an i/o line 8-bit programmable timer/event counter with overflow interrupt and 8-stage prescaler (tmr0) 16-bit programmable timer/event counter and overflow interrupts (tmr1) on-chip crystal and rc oscillator watchdog timer 8k 16 program memory 224 8 data memory ram pfd supported halt function and wake-up feature reduce power consumption 8-level subroutine nesting up to 1 s instruction cycle with 4mhz system clock at v dd =3v bit manipulation instruction 16-bit table read instruction 63 powerful instructions all instructions in one or two machine cycles low voltage reset function 28-pin sop/ssop(209mil) package technical document tools information faqs application note ha0016e writing and reading to the ht24 eeprom with the ht48 mcu series ha0018e controlling the ht1621 lcd controller with the ht48 mcu series ha0041e using the ht48ca0 to generate the ht6221 output signals ha0075e mcu reset and oscillator circuits application note ha0076e ht48rax/ht48cax software application note ha0082e ht48xa0-1 and ht48xa0-2 power-on reset timing
block diagram pin assignment ht48ra1/HT48CA1 rev. 1.30 2 october 12, 2007

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pin description pin name i/o rom code option description pa0~pa7 i/o wake-up* pull-high*** bidirectional 8-bit input/output port. each bit can be configured as a wake-up in - put by a option. software instructions determine the cmos output or schmitt trig - ger input with/without pull-high resistor. the pull-high resistor of each input/output line is also optional. pb0/pfd pb1~pb7 i/o pull-high** pb0 or pfd bidirectional 8-bit input/output port. software instructions determine the cmos output or schmitt trigger input with/without pull-high resistor. the pull-high resis - tor of each input/output line is also optional. the output mode of pb0 can be used as an internal pfd signal output and it can be used as a various frequency carrier signal. pc0/tmr0 pc1~pc4 pc5/tmr1 i/o pull-high* bidirectional 6-bit input/output port. software instructions determine the cmos output or schmitt trigger input with/without pull-high resistor. the pull-high resis - tor of each input/output line is also optional. pc0 and pc5 are pin shared with tmr0 and tmr1 function pins. pf0/int i/o pull-high* bidirectional 1-bit input/output port. software instructions determine the cmos output or schmitt trigger input with/without pull-high resistor. the pull-high resis - tor of this input/output line is also optional. pf0 is pin shared with the int func - tion pin. osc1 osc2 i o crystal or rc osc1, osc2 are connected to an rc network or crystal (determined by option) for the internal system clock. in the case of rc operation, osc2 is the output terminal for 1/4 system clock. res i schmitt trigger reset input, active low. vss negative power supply, ground vdd positive power supply note: * bit option ** nibble option *** byte option absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +6.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 40 cto85 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. ht48ra1/HT48CA1 rev. 1.30 3 october 12, 2007
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.0 5.5 v i dd1 operating current 3v no load, f sys =4mhz 0.6 1.5 ma 5v 24ma i dd2 operating current (crystal osc, rc osc) 5v no load, f sys =8mhz 48ma i stb1 standby current (wdt enabled and wdt rc osc on) 3v no load, system halt 1.1 5 a 5v 410 a i stb2 standby current (wdt disabled) 3v no load, system halt 0.1 1 a 5v 0.2 2 a v il1 input low voltage for i/o ports 0 0.3v dd v v ih1 input high voltage for i/o ports 0.7v dd v dd v v il2 input low voltage (res ) 0 0.4v dd v v ih2 input high voltage (res ) 0.9v dd v dd v v lvr low voltage reset lvr=2.0v 1.8 1.9 2.0 v lvr=3.0v 2.7 3.0 3.3 v i ol i/o port sink current 3v v ol =0.1v dd 48 ma 5v 10 20 ma i oh i/o port source current 3v v oh =0.9v dd 2 4 ma 5v 5 10 ma r ph pull-high resistance 3v 20 60 100 k 5v 10 30 50 k ht48ra1/HT48CA1 rev. 1.30 4 october 12, 2007
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 2.0v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f sys2 system clock (rc osc) 2.0v~5.5v 400 4000 khz 3.3v~5.5v 400 8000 khz f timer timer i/p frequency (tmr0/tmr1) 3v 50% duty 0 4000 khz 5v 0 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 32 65 130 s t wdt1 watchdog time-out period (wdt osc) 3v without wdt prescaler 11 23 46 ms 5v 8 17 33 ms t wdt2 watchdog time-out period (f sys /4) without wdt prescaler 1024 t sys t res external reset low pulse width 1 s t sst system start-up timer period power-up reset or wake-up from halt 1024 t sys t lvr low voltage width to reset 1 ms t int interrupt pulse width 1 s t acc data rom access time 1 s note: t sys =1/(f sys ) ht48ra1/HT48CA1 rev. 1.30 5 october 12, 2007
ht48ra1/HT48CA1 rev. 1.30 6 october 12, 2007 functional description execution flow the system clock for the mcu is derived from either a crystal or an rc oscillator. the system clock is internally divided into four non-overlapping clocks. one instruc - tion cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute in a cycle. if an instruction changes the program counter, two cycles are required to complete the instruction. program counter pc the program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a full range of pro - gram memory. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading register, subroutine call or return from subroutine, initial reset, internal interrupt, external inter - rupt or return from interrupts, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instructions. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed to the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within the current program rom page. when a control transfer takes place, an additional dummy cycle is required. * 1 4 4 6 7 8 ( * 4 4 6 9 7 * 1 4 4 6 : 7 8 ( * 4 4 6 7 * 1 4 4 6 : 7 8 ( * 4 4 6 : 7 : : . * ' 4 " % ; 4 6 4 % ) " . 7 execution flow mode program counter *12~*8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 00000 00000000 external interrupt 00000 00000100 timer/event counter 0 overflow 00000 00001000 timer/event counter 1 overflow 00000 00001100 skip program counter + 2 loading pcl *12~*8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #12~#8 #7 #6 #5 #4 #3 #2 #1 #0 return (ret, reti) s12~s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *12~*0: program counter bits s12~s0: stack register bits #12~#0: instruction code bits @7~@0: pcl bits
ht48ra1/HT48CA1 rev. 1.30 7 october 12, 2007 program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized into 8192 16 bits, addressed by the program counter and ta - ble pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for program initialization. after chip reset, the program always begins execution at lo - cation 000h. location 004h this area is reserved for the external interrupt service program. if the int input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at location 004h. location 008h this area is reserved for the timer/event counter 0 in - terrupt service program. if a timer interrupt results from a timer/event counter 0 overflow, and if the in - terrupt is enabled and the stack is not full, the program begins execution at location 008h . location 00ch this location is reserved for the timer/event counter 1 interrupt service program. if a timer interrupt results from a timer/event counter 1 overflow, and the inter- rupt is enabled and the stack is not full, the program begins execution at location 00ch. table location any location in the program memory can be used as look-up tables. the instructions tabrdc [m] (page specified by tbhp) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). the higher-order byte table pointer tbhp (1fh) and lower-order byte table pointer tblp (07h) are read/write registers, which indicate the table locations. before accessing the table, the location has to be placed in tbhp and tblp. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the ta - ble read instruction, the contents of tblh in the main routine are likely to be changed by the table read in - struction used in the isr. errors are thus brought about. given this, using the table read instruction in the main routine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both main routine and the isr, the in - terrupt(s) is supposed to be disabled prior to the table read instruction. it (they) will not be enabled until the tblh in the main routine has been backup. all table related instructions require 2 cycles to complete the operation. stack register stack this is a special part of the memory which is used to save the contents of the program counter (pc) only. the stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither read- able nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the pro - gram counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this feature prevents stack overflow al - lowing the programmer to use the structure more easily. in a similar case, if the stack is full and a call is sub - 4 < , * = ) = % & ! ' ' % . > , 4 ) , * , ! " , ? ! * , % ) 4 % & ! ' 8 * ) ! " 4 ) * ( + * 4 ( < % ( * , ) , ' > ) * 4 % ( ) * 4 ) * ( + * 4 ( < % ( * , ) 4 0 % % ; 9 ( + 4 ! < " 4 6 4 @ % / 7 0 % % ; 9 ( + 4 ! < " 4 6 4 @ % / 7 % * a 4 ) 4 ! ) & 4 # % ' 4 4 * % 4 = ) = = = = , ' > ) * 4 % ( ) * 4 ) * ( + * 4 ( < % ( * , ) 4 program memory instruction table location *12~*8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] tbhp @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 11111 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *12~*0: table location bits @7~@0: table pointer bits
ht48ra1/HT48CA1 rev. 1.30 8 october 12, 2007 sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return ad - dresses are stored). data memory ram the data memory is designed with 249 8 bits. the data memory is divided into two functional groups: special function registers and general purpose data memory (224 8). most are read/write, but some are read only. the special function registers include the indirect ad - dressing registers (r0;00h, r1;02h), timer/event counter 0 (tmr0;0dh), timer/event counter 0 control register (tmr0c;0eh), timer/event counter 1 higher order byte register (tmr1h;0fh), timer/event coun - ter 1 lower order byte register (tmr1l;10h), timer/event counter 1 control register (tmr1c;11h), program counter lower-order byte register ( pcl ;06h), memory pointer registers (mp0;01h, mp1;03h), accu - mulator ( acc ;05h), table pointer (tblp;07h, tbhp; 1fh), table higher-order byte register (tblh;08h), sta - tus register (status;0ah), interrupt control register (intc;0bh), watchdog timer option setting register (wdts;09h), i/o registers (pa;12h, pb;14h, pc;16h, pf;1ch), and i/o control registers (pac;13h, pbc;15h, pcc;17h, pfc;1dh). the remaining space before the 20h is reserved for future expanded usage and reading these locations will get 00h . the general purpose data memory, addressed from 20h to ffh, is used for data and control information under instruction commands. all of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly. except for some dedicated bits, each bit in the data memory can be set and reset by set [m].i and clr [m].i . they are also indirectly accessible through memory pointer registers (mp0 or mp1). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] ([02h]) will access data memory pointed to by mp0 (mp1). reading location 00h (02h) itself indi - rectly will return the result 00h. writing indirectly results in no operation. the memory pointer registers (mp0 and mp1) are 8-bit registers. accumulator the accumulator is closely related to alu operations. it is also mapped to location of the data memory and can carry out immediate data operations. the data move - ment between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic opera - tions. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) increment and decrement (inc, dec) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. 2 ) ! " 4 ( + % 4 $ 6 4 . * 7 + , ! " 4 ( + % 4 $ = = = = = = = = =
= = = = = = = = = = = = = = = =
= = = = = = = = a 4 ) ( / ! / 4 ! 4 b b = ) / , * 4 / / , ) & 4 & , * 4 ) / , * 4 / / , ) & 4 & , * 4 0 0 0 = 3 = 0 = ram mapping
ht48ra1/HT48CA1 rev. 1.30 9 october 12, 2007 status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf), and watchdog time-out flag (to). it also records the status information and controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addi - tion operations related to the status register may give different results from those intended. the to flag can be affected only by system power-up, a wdt time-out or executing the clr wdt or halt in - struction. the pdf flag can be affected only by exe - cuting the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or exe - cuting the subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status are important and if the subroutine can cor - rupt the status register, precautions must be taken to save it properly. interrupt the device provides an external interrupt and internal timer/event counter interrupts. the interrupt control register (intc;0bh) contains the interrupt control bits to set the enable/disable and the interrupt request flags. once an interrupt subroutine is serviced, all the other in- terrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter - rupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc may be set to allow interrupt nesting. if the stack is full, the inter - rupt request will not be acknowledged, even if the re - lated interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be pre - vented from becoming full. all these kinds of interrupts have a wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the pro - gram memory. only the program counter is pushed onto the stack. if the contents of the register or status register (status) are altered by the interrupt service program which corrupts the desired control sequence, the con - tents should be saved in advance. external interrupts are triggered by a high to low transi - tion of the int and the related interrupt request flag (eif; bit 4 of intc) will be set. when the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer/event counter 0 interrupt is initial - ized by setting the timer/event counter 0 interrupt re - quest flag (t0f; bit 5 of intc), caused by a timer 0 overflow. when the interrupt is enabled, the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (t0f) will be reset and the emi bit cleared to disable further in- terrupts. the internal timer/even counter 1 interrupt is initialized by setting the timer/event counter 1 interrupt request flag (t1f;bit 6 of intc), caused by a timer 1 overflow. when the interrupt is enabled, the stack is not full and the t1f is set, a subroutine call to location 0ch will oc - cur. the related interrupt request flag (t1f) will be reset and the emi bit cleared to disable further interrupts. bit no. label function 0c c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared by system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register
ht48ra1/HT48CA1 rev. 1.30 10 october 12, 2007 during the execution of an interrupt subroutine, other in - terrupt acknowledge signals are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, ret or reti may be invoked. reti will set the emi bit to enable an in - terrupt service, but ret will not. interrupts, occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding inter - rupts are enabled. in the case of simultaneous requests the following table shows the priority that is applied. these can be masked by resetting the emi bit. interrupt source priority vector external interrupt 1 04h timer/event counter 0 overflow 2 08h timer/event counter 1 overflow 3 0ch the timer/event counter 0/1 interrupt request flag (t0f/t1f), external interrupt request flag (eif), enable timer/event counter 0/1 interrupt bit (et0i/et1i), en - able external interrupt bit (eei) and enable master inter - rupt bit (emi) constitute an interrupt control register (intc) which is located at 0bh in the data memory. emi, eei, et0i and et1i are used to control the enabling/dis- abling of interrupts. these bits prevent the requested in- terrupt from being serviced. once the interrupt request flags (t0f, t1f, eif) are set, they will remain in the intc register until the interrupts are serviced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. in- terrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. if only one stack is left and enabling the interrupt is not well con trolled, the original control sequence will be dam - aged once the call operates in the interrupt subrou - tine. oscillator configuration there are 2 oscillator circuits implemented in the microcontroller. both of them are designed for system clocks, namely the rc oscillator and the crystal oscillator, which are de - termined by options. no matter what oscillator type is selected, the signal provides the system clock. the halt mode stops the system oscillator and resists the external signal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vss is required and the resistance should range from 100k to 820k . the system clock, divided by 4, is available on osc2, which can be used to syn - chronize external logic. the internal rc oscillator pro - vides the most cost effective solution. however, the frequency of oscillation may vary with vdd, tempera - tures and the chip itself due to process variations. it is, therefore, not suitable for timing sensitive operations where an accurate oscillator frequency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are demanded. instead of a crystal, the resonator can also be connected between osc1 and osc2 to get a frequency reference, but two external ca- pacitors in osc1 and osc2 are required. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works with a period of approximately 90 s. the wdt oscillator can be disabled by rom code option to conserve power. bit no. label function 0 emi controls the master (global) interrupt (1=enabled; 0=disabled) 1 eei controls the external interrupt (1=enabled; 0=disabled) 2 et0i controls the timer/event counter 0 interrupt (1=enabled; 0=disabled) 3 et1i controls the timer/event counter 1 interrupt (1=enabled; 0=disabled) 4 eif external interrupt request flag (1=active; 0=inactive) 5 t0f internal timer/event counter 0 request flag (1=active; 0=inactive) 6 t1f internal timer/event counter 1 request flag (1=active; 0=inactive) 7 unused bit, read as 0 intc (0bh) register . * ! " 4 , " " ! * % 4 , " " ! * % 4 + ) 4 ! , ) # $ system oscillator
ht48ra1/HT48CA1 rev. 1.30 11 october 12, 2007 watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator), instruction clock (system clock divided by 4), determines the rom code option. this timer is designed to prevent a software malfunction or sequence from jumping to an unknown location with unpredictable results. the watchdog timer can be dis - abled by rom code option. if the watchdog timer is dis - abled, all the executions related to the wdt result in no operation. once the internal wdt oscillator (rc oscillator with a period of 90 s@3v normally) is selected, it is first di - vided by 256 (8-stage) to get the nominal time-out pe - riod of 23ms@3v. this time-out period may vary with temperatures, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be real - ized. writing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1, and ws0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.9s@3v seconds. if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and oper - ates in the same manner except that in the halt state the wdt may stop counting and lose its protecting pur - pose. in this situation the logic can only be restarted by external logic. the high nibble and bit 3 of the wdts are reserved for user s defined flags, which can be used to indicate some specified status. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom- mended, since the halt will stop the system clock. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts register the wdt overflow under normal operation will initialize chip reset and set the status bit to . but in the halt mode, the overflow will initialize a warm reset and only the program counter and sp are reset to zero. to clear the contents of wdt (including the wdt prescaler), three methods are adopted; external reset (a low level to res ), software instruction and a halt instruction. the software instruction include clr wdt and the other set clr wdt1 and clr wdt2 . of these two types of instruction, only one can be active depending on the rom code option clr wdt times selection option. if the clr wdt is selected (i.e. clr wdt times equal one), any execution of the clr wdt in - struction will clear the wdt. in the case that clr wdt1 and clr wdt2 are chosen (i.e. clr wdt times equal two), these two instructions must be exe - cuted to clear the wdt; otherwise, the wdt may reset the chip as a result of time-out. power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator will be turned off but the wdt oscillator remains running (if the wdt oscillator is se - lected). the contents of the on chip ram and registers remain unchanged. wdt and wdt prescaler will be cleared and re- counted again (if the wdt clock is from the wdt os- cillator). all of the i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge sig - nal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow per - forms a warm reset . after the to and pdf flags are examined, the reason for chip reset can be determined. the pdf flag is cleared by system power-up or execut - ing the clr wdt instruction and is set when execut - ing the halt instruction. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and sp; the others remain in their original status. . * ' 4 " % ; 9 < , * 4 % ( ) * 3 4 ! " 9 < , * 4 % ( ) * 9 * % 9 4 3 4 , ' 9 % ( * 3 5 3 % / + * , % ) " * 3 watchdog timer
ht48ra1/HT48CA1 rev. 1.30 12 october 12, 2007 the port a wake-up and interrupt methods can be con - sidered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by mask option. awakening from an i/o port stim - ulus, the program will resume execution of the next in - struction. if it awakens from an interrupt, two sequence may occur. if the related interrupt is disabled or the inter - rupt is enabled but the stack is full, the program will re - sume execution at the next instruction. if the interrupt is enabled and the stack is not full, the regular interrupt re - sponse takes place. if an interrupt request flag is set to 1 before entering the halt mode, the wake-up func - tion of the related interrupt will be disabled. once a wake-up event occurs, it takes 1024 t sys (system clock period) to resume normal operation. in other words, a dummy period will be inserted after a wake-up. if the wake-up results from an interrupt acknowledge signal, the actual interrupt subroutine execution will be delayed by one or more cycles. if the wake-up results in the next instruction execution, this will be executed immediately after the dummy period is finished. to minimize power consumption, all the i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm re - set that resets only the program counter and sp, leav- ing the other circuits in their original state. some regis- ters remain unchanged during other reset conditions. most registers are reset to the initial condition when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different chip resets . to pdf reset conditions 0 0 res reset during power-up u u res reset during normal operation 0 1 res wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u stands for unchanged to guarantee that the system oscillator is started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem reset (power-up, wdt time-out or res reset) or the system awakes from the halt state. when a system reset occurs, the sst delay is added during the reset period. any wake-up from halt will en - able the sst delay. the functional unit chip reset status are shown below. program counter 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer/event counter off input/output ports input mode stack pointer points to the top of the stack * 4 , ' 9 % ( * 1 , + 4 4 * reset timing chart ; ; c c ; c reset circuit note: most applications can use the basic reset cir - cuit as shown, however for applications with ex- tensive noise, it is recommended to use the hi-noise reset circuit. 3 ! ' 4 * 3 = 0 % " / * . * ' 4 * 9 < , * 4 , + + " % ( ) * reset configuration
ht48ra1/HT48CA1 rev. 1.30 13 october 12, 2007 the states of the registers is summarized in the table. register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt)* mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 0000h 0000h 0000h 0000h 0000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr0c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu tmr1h xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1l xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu tmr1c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu pcc --11 1111 --11 1111 --11 1111 --11 1111 --uu uuuu pf ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u pfc ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u note: * stands for warm reset u stands for unchanged x stands for unknown
ht48ra1/HT48CA1 rev. 1.30 14 october 12, 2007 timer/event counter two timer/event counters (tmr0, tmr1) are imple - mented in the device. the timer/event counter 0 con - tains an 8-bit programmable count-up counter and the clock may come from an external source or the system clock. the timer/event counter 1 contains an 16-bit programmable count-up counter and the clock may come from an external source or the system clock di - vided by 4. of the two timer/event counters, using external clock in - put allows the user to count external events, measure time internals or pulse widths, or generate an accurate time base. while using the internal clock allows the user to generate an accurate time base. only the timer/event counter 0 can generate pfd sig - nal by using external or internal clock, and pfd fre - quency is determine by the equation f int /[2 (256-n)]. there are 2 registers related to timer/event counter 0; tmr0(0dh), tmr0c(0eh). in timer/event counter 0 counting mode (t0on=1), writing tmr0 will only put the written data to preload register (8 bits). the timer/event counter 0 preload register is changed by each writing tmr0 operations. reading tmr0 will also latch the tmr0 to the destination. the tmr0c is the timer/event counter 0 control register, which defines the operating mode, counting enable or disable and active edge. the t0m0, t0m1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr0) pin. the timer mode functions as a normal timer with the clock source coming from the f int clock. the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr0). the counting is based on the f int clock. in the event count or timer mode, once the timer/event counter 0 starts counting, it will count from the current contents in the timer/event counter 0 to ffh. once overflow occurs, the counter is reloaded from the timer/event counter 0 preload register and generates the corresponding interrupt request flag (t0f; bit 5 of intc) at the same time. in pulse width measurement mode with the t0on and t0e bits are equal to one, once the tmr0 has received a transition from low to high (or high to low if the t0e bit is 0) it will start counting until the tmr0 returns to the original level and reset the t0on. the measured result will remain in the timer/event counter 0 even if the acti - vated transition occurs again. in other words, only one cycle measurement can be done. until setting the t0on, the cycle measurement will function again as long as it receives further transition pulse. note that, in this operating mode, the timer/event counter 0 starts counting not according to the logic level but according to the transition edges. in the case of counter overflows, the counter 0 is reloaded from the timer/event counter 0 preload register and issues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit(t0on; bit 4 of tmr0c) should be set to 1. in the pulse width measurement mode, the t0on will be cleared automatically after the measurement cycle is complete. but in the other two modes the t0on can only be reset by instructions. the overflow of the timer/event counter 0 is one of the wake-up sources. no matter what the operation mode is, writin ga0to et0i can disabled the corresponding interrupt service. in the case of timer/event counter 0 off condition, writing data to the timer/event counter 0 preload regis - ter will also load the data to timer/event counter 0. but if the timer/event counter 0 is turned on, data written to the timer/event counter 0 will only be kept in the timer/event counter 0 preload register. the timer/event counter 0 will still operate until the overflow occurs (a timer/event counter 0 reloading will occur at the same time). when the timer/event counter 0 (reading tmr0) is read, the clock will be blocked to avoid errors. as this may results in a counting error, this must be taken into consideration by the programmer. the bit 0~2 of the tmr0c can be used to define the pre-scaling stages of the internal clock sources of timer/event counter 0. the definitions are as shown. bit no. label function 0 1 2 t0psc0 t0psc1 t0psc2 to define the prescaler stages, t0psc2, t0psc1, t0psc0= 000: f int =f sys /2 001: f int =f sys /4 010: f int =f sys /8 011: f int =f sys /16 100: f int =f sys /32 101: f int =f sys /64 110: f int =f sys /128 111: f int =f sys /256 3 t0e to define the tmr0 active edge of timer/event counter 0 (0=active on low to high; 1=active on high to low) 4 t0on to enable/disable timer 0 counting (0=disabled; 1=enabled) 5 unused bit, read as 0 6 7 t0m0 t0m1 to define the operating mode (t0m1, t0m0) 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr0c (0eh) register
ht48ra1/HT48CA1 rev. 1.30 15 october 12, 2007 there are 3 registers related to timer/event counter 1; tmr1h(0fh), tmr1l(10h), tmr1c(11h). writing tmr1l will only put the written data to an internal lower-order byte buffer (8 bits) and writing tmr1h will transfer the specified data and the contents of the lower-order byte buffer to tmr1h and tmr1l preload registers, respectively. the timer/event counter 1 preload register is changed by each writing tmr1h op - erations. reading tmr1h will latch the contents of tmr1h and tmr1l counters to the destination and the lower-order byte buffer, respectively. reading the tmr1l will read the contents of the lower-order byte buffer. the tmr1c is the timer/event counter 1 control register, which defines the operating mode, counting en - able or disable and active edge. the t1m0, t1m1 bits define the operating mode. the event count mode is used to count external events, which means the clock source comes from an external (tmr1) pin. the timer mode functions as a normal timer with the clock source coming from the instruction clock. the pulse width measurement mode can be used to count the high or low level duration of the external signal (tmr1). the counting is based on the instruction clock. in the event count or timer mode, once the timer/event counter 1 starts counting, it will count from the current contents in the timer/event counter 1 to ffffh. once overflow occurs, the counter is reloaded from the timer/event counter 1 preload register and generates the corresponding interrupt request flag (t1f; bit 6 of intc) at the same time. in pulse width measurement mode with the t1on and t1e bits are equal to one, once the tmr1 has received a transition from low to high (or high to low if the t1e bit is 0) it will start counting until the tmr1 returns to the original level and reset the t1on. the measured result will remain in the timer/event counter 1 even if the acti - vated transition occurs again. in other words, only one cycle measurement can be done. until setting the t1on, the cycle measurement will function again as long as it receives further transition pulse. note that, in this operating mode, the timer/event counter 1 starts counting not according to the logic level but according to the transition edges. in the case of counter overflows, the counter 1 is reloaded from the timer/event counter 1 preload register and issues the interrupt request just like the other two modes. to enable the counting operation, the timer on bit (t1on; bit 4 of tmr1c) should be set to 1. in the pulse width measurement mode, the t1on will be cleared au - tomatically after the measurement cycle is complete. but in the other two modes the t1on can only be reset by instructions. the overflow of the timer/event coun - ter 1 is one of the wake-up sources. no matter what the operation mode is, writin ga0to et1i can disabled the corresponding interrupt service. in the case of timer/event counter 1 off condition, writing data to the timer/event counter 1 preload regis- ter will also load the data to timer/event counter 1. but if the timer/event counter 1 is turned on, data written to the timer/event counter 1 will only be kept in the ( " 4 3 , / * 1 ! ( ' ) * % / 4 % ) * % " , ' > ) * 4 % ( ) * 4 " % ! / 4 & , * 9 < , * , ' > ) * 4 % ( ) * 6 7 ! * ! 4 ( " % ! / 9 * ! & 4 ! " 9 4 # $ # 5 6 5 7 > # " % @ 4 * % 4 ) * ( + * timer/event counter 0 ( " 4 3 , / * 1 ! ( ' ) * % / 4 % ) * % " 9 < , * , ' > ) * 4 % ( ) * " % ! / 4 & , * ! * ! 4 ( " % ! / > # " % @ 4 * % 4 ) * ( + * 9 < , * , ' > ) * 4 % ( ) * 6 = 0 7 0 % @ 4 . * ( # # # $ timer/event counter 1
ht48ra1/HT48CA1 rev. 1.30 16 october 12, 2007 timer/event counter 1 preload register. the timer/event counter 1 will still operate until the overflow occurs (a timer/event counter 1 reloading will occur at the same time). when the timer/event counter 1 (reading tmr1h) is read, the clock will be blocked to avoid errors. as this may results in a counting error, this must be taken into consideration by the programmer. the definitions of the tmr1c are as shown. bit no. label function 0~2 unused bit, read as 0 3 t1e to define the active edge of tmr1 pin input signal (0/1: active on low to high/high to low) 4 t1on to enable/disable timer 1 counting (0/1: disabled/enabled) 5 unused bit, read as 0 6 7 t1m0 t1m1 to define the operating mode (t1m1, t1m0) 01=event count mode (external clock) 10=timer mode (internal clock) 11=pulse width measurement mode 00=unused tmr1c (11h) register input/output ports there are 23 bi-directional input/output lines in the mi - cro-controller, labeled from pa to pc and pf, which are mapped to the data memory of [12h], [14h], [16h] and [1ch], respectively. all of these i/o ports can be used as input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m = 12h, 14h, 16h or 1ch). for output operation, all the data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pfc) to control the input/output configuration. with this control register, cmos output or schmitt trig - ger input with or without (depends on options) pull-high resistor structures can be reconfigured dynamically (i.e., on-the fly) under software control. to function as an in - put, the corresponding latch of the control register has to be set as 1 . the pull-high resistor (if the pull-high re - sistor is enabled) will be exhibited automatically. the in - put sources also depends on the control register. if the control register bit is 1 , the input will read the pad state ( mov and read-modify-write instructions?). if the con - trol register bit is 0, the contents of the latches will move to internal data bus ( mov and read-modify-write in - structions). the input paths (pad state or latches) of read-modify-write instructions are dependent on the control register bits. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h, 17h and 1dh. 5 5 5 6 4 % ) " . 7 4 3 ! ; 9 ( + 4 + * , % ) 4 # % 4 4 ) " . . * ' 4 3 ! ; 9 ( + 4 6 4 % ) " . 7 ! / 4 ! * ! 4 & , * 6 4 % ) " . 7 d - d d - d % ) * % " 4 , * ! * ! 4 ( 3 , * 4 % ) * % " 4 & , * 1 , + 4 * ! / 4 % ) * % " 4 & , * 3 , * 4 ! * ! 4 & , * ! * ! 4 , * 4 # % 4 4 ) " . e 4 % ) * % " f 4 ! * ! 4 & , * input/output ports
ht48ra1/HT48CA1 rev. 1.30 17 october 12, 2007 after a chip reset, these input/output lines stay at high levels (pull-high options) or floating state (non-pull-high options). each bit of these input/output latches can be set or cleared by set [m].i (m=12h, 14h, 16h or 1ch) instructions. some instructions first input data and then follow the output operations. for example, set [m].i , clr [m].i , cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the ac - cumulator. each line of port a has the capability of waking-up the device. the highest 2 bits of port c and 7 bits of port f are not physically implemented; on reading them a 0 is returned whereas writing then results in a no-operation. pull-high resistors of each port are decided by a option bit. the pb0 is pin-shared with pfd signal, respectively. if the pfd option is selected, the output signal in output mode of pb0 will be the pfd signal. the input mode al - ways remain its original functions. the pf0 and pc0 are pin-shared with int and tmr0. the int signal is di - rectly connected to pf0. the pfd output signal (in out - put mode) are controlled by the pb0 data register only. the truth table of pb0/pfd is listed below. pbc (15h) bit0 i o o o pb0/pfd option x pb0 pfd pfd pb0 (14h) bit0 x d 0 1 pb0 pad status i d 0 pfd note: i input o output d data low voltage reset lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as changing a battery, the lvr will au - tomatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in their original state to exceed 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. c c c
0 c 0 c
* 4 , & ) ! " * g g % ' ! " 4 + ! * , % ) * 0 4 * * 4 % " * ! & low voltage reset note: *1 to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2 since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode.
ht48ra1/HT48CA1 rev. 1.30 18 october 12, 2007 options the following table shows all kinds of code option in the mcu. all of the mask options must be defined to ensure proper system functioning. function pa0~pa7 wake-up enable or disable options pc pull-high enable or disable pa pull-high enable or disable: byte option pf pull-high enable or disable pb pull-high (pb0~pb3, pb4~pb7) enable or disable: nibble option pb0 or pfd clr wdt instructions system oscillators: rc or crystal wdt enable or disable wdt clock source: wdtosc or system clock/4 lvr function: enable or disable lvr voltage: 2.0v or 3.0v
application circuits note: 1. crystal/resonator system oscillators for crystal oscillators, c1 and c2 are only required for some crystal frequencies to ensure oscillation. for resonator applications c1 and c2 are normally required for oscillation to occur. for most applications it is not necessary to add r1. however if the lvr function is disabled, and if it is required to stop the oscillator when v dd falls below its operating range, it is recommended that r1 is added. the values of c1 and c2 should be selected in consultation with the crystal/resonator manufacturer specifications. 2. reset circuit the reset circuit resistance and capacitance values should be chosen to ensure that vdd is stable and re- mains within its operating voltage range before the res pin reaches a high level. ensure that the length of the wiring connected to the res pin is kept as short as possible, to avoid noise interference. 3. for applications where noise may interfere with the reset circuit and for details on the oscillator external components, refer to application note ha0075e for more information. ht48ra1/HT48CA1 rev. 1.30 19 october 12, 2007 5 5 5 , ( , * c ; c

; h h ; # $ +
% 4 e 4 e 4 4 4 ) % *
example ht48ra1/HT48CA1 rev. 1.30 20 october 12, 2007 6 0 ! ) , ) & 4 ) + ( * 7 , > c ; c 5 ; , ( , * < ! *
ht48ra1/HT48CA1 rev. 1.30 31 october 12, 2007 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht48ra1/HT48CA1 rev. 1.30 32 october 12, 2007 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht48ra1/HT48CA1 rev. 1.30 33 october 12, 2007 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc
acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m]
acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc
acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc
acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m]
acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc
acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc
acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m]
acc and [m] affected flag(s) z ht48ra1/HT48CA1 rev. 1.30 34 october 12, 2007
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack
program counter + 1 program counter
addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m]
00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i
0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to
0 pdf
0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to
0 pdf
0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to
0 pdf
0 affected flag(s) to, pdf ht48ra1/HT48CA1 rev. 1.30 35 october 12, 2007
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously containe d a 1 are changed to 0 and vice versa. operation [m]
[m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc
[m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m]
acc + 00h or [m]
acc + 06h or [m]
acc + 60h or [m]
acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m]
[m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc
[m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to
0 pdf
1 affected flag(s) to, pdf ht48ra1/HT48CA1 rev. 1.30 36 october 12, 2007
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m]
[m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc
[m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter
addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc
[m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc
x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m]
acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc
acc or [m] affected flag(s) z ht48ra1/HT48CA1 rev. 1.30 37 october 12, 2007
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc
acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m]
acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter
stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter
stack acc
x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter
stack emi
1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1)
[m].i; (i = 0~6) [m].0
[m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1)
[m].i; (i = 0~6) acc.0
[m].7 affected flag(s) none ht48ra1/HT48CA1 rev. 1.30 38 october 12, 2007
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1)
[m].i; (i = 0~6) [m].0
c c
[m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1)
[m].i; (i = 0~6) acc.0
c c
[m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i
[m].(i+1); (i = 0~6) [m].7
[m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i
[m].(i+1); (i = 0~6) acc.7
[m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i
[m].(i+1); (i = 0~6) [m].7
c c
[m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i
[m].(i+1); (i = 0~6) acc.7
c c
[m].0 affected flag(s) c ht48ra1/HT48CA1 rev. 1.30 39 october 12, 2007
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc
acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m]
acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m]
[m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc
[m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m]
ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i
1 affected flag(s) none ht48ra1/HT48CA1 rev. 1.30 40 october 12, 2007
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m]
[m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc
[m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc
acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m]
acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc
acc x affected flag(s) ov, z, ac, c ht48ra1/HT48CA1 rev. 1.30 41 october 12, 2007
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0
[m].7 ~ [m].4 acc.7 ~ acc.4
[m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc
[m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m]
program code (low byte) tblh
program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m]
program code (low byte) tblh
program code (high byte) affected flag(s) none ht48ra1/HT48CA1 rev. 1.30 42 october 12, 2007
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc
acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m]
acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc
acc xor x affected flag(s) z ht48ra1/HT48CA1 rev. 1.30 43 october 12, 2007
package information 28-pin sop (300mil) outline dimensions symbol dimensions in mil min. nom. max. a 394 419 b 290 300 c14 20 c 697 713 d92 104 e 50 f4 g32 38 h4 12 0 10 ht48ra1/HT48CA1 rev. 1.30 44 october 12, 2007 i 2 =
28-pin ssop (209mil) outline dimensions symbol dimensions in mil min. nom. max. a 291 323 b 196 220 c9 15 c 396 407 d65 73 e 25.59 f4 10 g26 34 h4 8 0 8 ht48ra1/HT48CA1 rev. 1.30 45 october 12, 2007 i 2 =
product tape and reel specifications reel dimensions sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330 1.0 b reel inner diameter 62 1.5 c spindle hole diameter 13.0+0.5 0.2 d key slit width 2.0 0.5 t1 space between flange 24.8+0.3 0.2 t2 reel thickness 30.2 0.2 ht48ra1/HT48CA1 rev. 1.30 46 october 12, 2007
carrier tape dimensions sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.0 0.3 p cavity pitch 12.0 0.1 e perforation position 1.75 0.1 f cavity to perforation (width direction) 11.5 0.1 d perforation diameter 1.5+0.1 d1 cavity hole diameter 1.5+0.25 p0 perforation pitch 4.0 0.1 p1 cavity to perforation (length direction) 2.0 0.1 a0 cavity length 10.85 0.1 b0 cavity width 18.34 0.1 k0 cavity depth 2.97 0.1 t carrier tape thickness 0.35 0.01 c cover tape width 21.3 ht48ra1/HT48CA1 rev. 1.30 47 october 12, 2007 3 * -
ht48ra1/HT48CA1 rev. 1.30 48 october 12, 2007 copyright 2007 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shanghai sales office) 7th floor, building 2, no.889, yi shan rd., shanghai, china 200233 tel: 86-21-6485-5560 fax: 86-21-6485-0313 http://www.holtek.com.cn holtek semiconductor inc. (shenzhen sales office) 5/f, unit a, productivity building, cross of science m 3rd road and gaoxin m 2nd road, science park, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor inc. (beijing sales office) suite 1721, jinyu tower, a129 west xuan wu men street, xicheng district, beijing, china 100031 tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 fax: 86-10-6641-0125 holtek semiconductor inc. (chengdu sales office) 709, building 3, champagne plaza, no.97 dongda street, chengdu, sichuan, china 610016 tel: 86-28-6653-6590 fax: 86-28-6653-6591 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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